Silicon-On-Insulator (SOI) semiconductor devices are of increasing interest in present and future semiconductor manufacturing, for example, in the context of the Complementary Metal Oxide Semiconductor (CMOS) technology. The buried SiO2 (BOX) layer of the SOI structure is conventionally formed by oxygen ion implantation beneath the surface of a silicon wafer followed by an anneal process at typical anneal temperatures of some 1300° C. to 1400° C. In some applications there is a need for providing a patterned BOX structure. Usually, ion implantation is facilitated by a correspondingly patterned implantation mask in order to obtained such patterned BOX structures.
The manufacture of such structures is problematic. First of all, defects form at a relatively high density at the mask edge regions. Also, in order to obtain BOX structures with two or more BOX thicknesses, a second implant using a second complementary implantation mask or more additional implantation processes facilitated by a number of complementary implantation masks are needed, thereby significantly increasing the number of processing steps of the overall manufacture. Misalignment of different BOX layers of different thicknesses formed by ion implantation proves to be a further problem affecting the performance of eventually finished semiconductor devices based on SOI structures.
Thus, despite recent engineering progresses, there is still a need for providing methods for the formation of SOI structures comprising multiple Si and/or BOX layers of different thicknesses that reliably allows for tuning the thicknesses of the layers under questions. The present invention now satisfies this need.